Cortex-M33 Exclusive Monitors: Behavior of LDREX/STREX on Internal SRAM vs. Peripherals for Atomic RMW

1. Peripheral space on Cortex-M33 is Device memory, normally shareable and execute-never. ARM says Device memory is the correct type for peripheral control registers because normal-memory optimisations can be unsafe for peripherals.

2. For Cortex-M33 specifically, ARM’s TRM says exclusive accesses to Device regions outside PPB behave like equivalent accesses to shared Normal memory, and all Device memory is shared in Armv8-M. But it also says the behaviour of external exclusive accesses depends on the global exclusive monitor in your system.

3. If the exclusive transaction is sent externally and there is no exclusive monitor for that memory region, ARM’s Cortex-M33 guide says STREX / STLEX fails.

4. PPB/core peripheral region is different: for 0xE0000000–0xE00FFFFF ARM says exclusive accesses do not update the internal local exclusive monitor, and STREX/STLEX status is always updated with 0, meaning it reports success like an ordinary store. That is not useful atomic locking.

Most likely in you observe the behaviour described in p.3

My conclusion: for Cortex-M33, LDREX/STREX on memory-mapped peripherals is not a good generic solution. It is only acceptable if the exact MCU/bus/peripheral region documents exclusive monitor support and the register itself is safe to read-modify-write. Otherwise use peripheral atomic set/clear registers or a short critical section.