AVX-512 MD5 implementation: unexplained performance regression on Zen 4

The critical path of calculating MD5 is essentially this (indented lines are outside the critical path):

    A+=M[g[i]]+K[i] // A was calculated 4 iterations ago
F=LOGIC[i](B,C,D)   // most critical dependency is B
F+=A
F=rot(F,s[i])
    A=D; D=C; C=B;  // just renaming variables
B+=F

This happens 64 times for each block, i.e., as long as LOGIC, ADD, ROT each have 1 cycle latency, one block can be processed in 4x64=256 cycles (+1 cycle, since the result of A,B,C,D is added to a0,...,d0).

If (as on Zen4) the vprold has a latency of 2 cycles, processing one block will take 5x64=320 cycles (again +1, for adding a0,...,d0).

Another thing, which llvm-mca seems to ignore is that (at least according to uops.info) the latency of vpternlogd is 1 only for the first operand, but 2 for the others. That means to recreate the results of llvm-mca, one has to make sure that the B operand is the first operand of vpternlogd.

I don't see anything obvious to circumvent this (i.e., the higher latency of vprold), except when s[i] is a multiple of 16, one could replace it by a vpshuflw (this unfortunately only happens when LOGIC[i](B,C,D) = B ^ (C ^ D), which could be calculated with just one cycle latency to B anyways).