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VeriGen: A Large Language Model for Verilog Code Generation

187
Citations
May 31, 2024
Published Date

Research Abstract & Technology Focus

In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by automatically completing partial Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks. We evaluate the functional correctness of the generated Verilog code using a specially designed test suite, featuring a custom problem set and testing benches. Here, our fine-tuned open-source CodeGen-16B model outperforms the commercial state-of-the-art GPT-3.5-turbo model with a 1.1% overall increase. Upon testing with a more diverse and complex problem set, we find that the fine-tuned model shows competitive performance against state-of-the-art gpt-3.5-turbo, excelling in certain scenarios. Notably, it demonstrates a 41% improvement in generating syntactically correct Verilog code across various problem categories compared to its pre-trained counterpart, highlighting the potential of smaller, in-house LLMs in hardware design automation. We release our training/evaluation scripts and LLM checkpoints as open-source contributions.
verigen large language model verilog generation
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What is the core focus of the research titled 'VeriGen: A Large Language Model for Verilog Code Generation'?

This literature focuses on: In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by automatically completing partial Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on ...

Are there open-source GitHub repositories related to VeriGen: A Large Language Model for Verilog Code Generation?

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Yes, highly correlated activity was mapped. An entry titled 'VeriGen: A Large Language Model for Verilog Code Generation' discusses this: In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by automatically completing partial Verilog co...

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Yes, highly correlated activity was mapped. An entry titled 'Velxio, Arduino Emulator' discusses this: Write, compile, and simulate Arduino sketches entirely in your browser. Real AVR8 CPU at 16 MHz, 48+ electronic components, Serial Monitor, and Lib...

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