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A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework.
Technical Positioning
A from-scratch exploration and re-implementation of historical scientific calculator CPU architecture, addressing the inefficiency of byte-oriented CPUs for BCD arithmetic.
SaaS Insight & Market Implications
This project represents a deep dive into fundamental hardware design, specifically addressing the architectural inefficiencies of standard byte-oriented CPUs for BCD arithmetic. While niche, the custom nibble-oriented CPU in Verilog demonstrates a commitment to optimizing for specific data types at the silicon level. The comprehensive scope, from ISA design to PCB implementation and multi-platform simulation (Verilator, Qt, WebAssembly), highlights the complexity and dedication required for low-level hardware development. This is not a direct SaaS play but showcases foundational engineering principles applicable to specialized embedded systems or custom silicon ventures where performance and resource efficiency for specific data operations are paramount. The project's educational and historical reconstruction value is significant, offering insights into specialized computing architectures.
Proprietary Technical Taxonomy
Raw Developer Origin & Technical Request
Hacker News
May 21, 2026
Show HN: A nibble-oriented CPU in Verilog to build a scientific calculator
The core question: how did HP's scientific calculators actually work at the gate level? That rabbit hole led to building one from scratch.The architectural decision everything else follows from: a decimal calculator should store numbers as BCD — one decimal digit per 4-bit nibble. A standard byte-oriented CPU (Z80, 6502) fights that layout constantly. So I designed a small custom CPU in Verilog where 4 bits is the natural data width and memory is nibble addressable.What the project covers:- Custom CPU: Harvard architecture, 12-bit ISA, 8-state execution
FSM, hardware stack guard with a FAULT state for microcode debugging- CORDIC for trig functions, verified to 14 significant digits- Two-pass assembler in Python (~700 lines)- Verilator + Qt framework: same Verilog source runs in simulation,
as a desktop GUI debugger, as WebAssembly, and on real hardware- Scripting language on top of the microcode for adding functions
without touching hardware- Custom PCB (EasyEDA/JLCPCB), battery, charging circuitWrite-up: baltazarstudios.comHackaday hackaday.com/2026/05/13/build-...
Developer Debate & Comments
This puts my poor little micropython calculator¹ to shame.1. https://git.sr.ht/~twentyafterfour/macro-calculator
One of the coolest projects I've seen in a while! Amazing work! In case anyone missed the write-up^1, it's very well-written. I really enjoyed the chapter about designing the instruction set.1: https://baltazarstudios.com/calculator-introduction/
Cool projectReally hoping that ghidra can add support for non-byte aligned memory regions some day. So many cool 4-bit architectures out there and attempting to shoehorn them into ghidra produces not great results
There is a WebAssembly version running online here, with and without debugger panel:https://baltazarstudios.com/files/calculator-d/Calculator.ht...https://baltazarstudios.com/files/calculator/Calculator.htmlThis WebAsm code is compiled using Qt and Verilator so it runs the "hardware" and its microcode inside the simple UI shell that provides the calc interface. In the debug version you can list the ucode, set breakpoints, see regs etc.
This is a brilliant project. (My DM42 returned 9 exactly.)Blog post 6 had an error where the picture of a HP-71B (I have one and used its Forth/Assembler ROM manual to write the first HP-48 ROM decoder) where the caption says it is a 48GX (both used a Saturn CPU).
Very impressive, and obviously a labour of love! As a calculator and SystemVerilog enthusiast, it's wonderful to see a project such as this come to fruition - congratulations!I'm holding in my hand a 4-bit Von Neumann Mostek MK50310N that my father and I used to use to build calculators long ago. Although Mostek made chips for HP (such as the HP-35), they weren't commercially available, but the 50310 was. We could only dream of a project such as yours. I was happy when the "open source" NumWorks was released, but this project aligns more with my interests.Will definitely install the Qt simulator - would be even better to build one IRL!
At least the 6502 has a BCD mode built in!
If the CPU is nibble-oriented, wouldn't that mean that that is its byte size?
My dad worked for HP from the mid-1970s through the mid-1990s. Needless to say, I used HP calculators in high school and college. The best things about having an HP calculator were the solid physical construction (the buttons on the 11C and 15C were awesome), the accuracy, and the fact that whenever your classmates asked to borrow your calculator they would recoil in horror when you asked them whether they knew RPN. Nobody borrowed my calculator. Anyway, I love this project.
Ironically the Z80 is a nibble ALU. That's why its so slow compared to the competition, an 8 bit add on a "2 MHz" Z80 takes as much clock time as a 8 bit add on a "1 MHz" 6809.
Frequently Asked Questions
Market intelligence mapped to A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework..
What is the technical positioning of A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework.?
Based on our AI analysis of the original developer request, its primary technical positioning is: A from-scratch exploration and re-implementation of historical scientific calculator CPU architecture, addressing the inefficiency of byte-oriented CPUs for BCD arithmetic.
How is the developer community reacting to A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework.?
Yes, we have tracked 42 direct responses and active debates regarding this specific topic originating from Hacker News.
Which technical concepts are associated with A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework.?
Our proprietary extraction maps A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework. to adjacent architectural concepts including Verilog, nibble-oriented CPU, gate level, BCD.
Are developers creating tools for A custom nibble-oriented CPU designed in Verilog, specifically for decimal arithmetic, implemented to build a scientific calculator. It includes a custom ISA, FSM, CORDIC for trig functions, an assembler, and a multi-platform simulation/debugging framework.?
Yes, open-source adoption is correlated. An active project titled 'fikrikarim/parlor' explores similar frameworks: On-device, real-time multimodal AI. Have natural voice and vision conversations with an AI that runs entirely on your machine. Powered by Gemma 4 E...
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