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Gemini Executive Synthesis

turbo3 and turbo4 quantization implementation, specifically related to block size changes and kernel instantiation.

Technical Positioning
Ensuring correct and robust implementation of different quantization schemes (turbo3, turbo4) across varying block sizes and head dimensions, preventing data corruption and out-of-bounds access.
SaaS Insight & Market Implications
A post-commit review identified critical bugs in the block size 32 change, corrupting turbo4 cache writes and causing out-of-bounds array access in CPU paths. The `SET_ROWS` kernel, hardcoded for turbo3, was incorrectly instantiated for turbo4, and integer division logic dropped tail blocks for non-128 head dimensions. This reveals significant fragility in low-level quantization implementations, where minor changes can introduce severe data integrity issues across different model configurations and quantization types. The reliance on specific head dimensions (e.g., Qwen's 128) masked a broader problem. Market implications include the necessity for rigorous, automated code analysis and comprehensive testing across diverse model architectures and hardware to ensure the reliability and compatibility of highly optimized, low-level inference components.
Proprietary Technical Taxonomy
block size 32 turbo4 non-128 head dims SET_ROWS kernel turbo3-specific 3-bit split block layout cache writes corrupted

Raw Developer Origin & Technical Request

Source Icon GitHub Issue Mar 25, 2026
Repo: TheTom/turboquant_plus
Post-commit review: block size 32 breaks turbo4 and non-128 head dims

## Codex post-commit review found 3 bugs in block size 32 change:

### 1. CRITICAL: SET_ROWS kernel is turbo3-specific but still instantiated for turbo4
The kernel_set_rows_turbo now hardcodes turbo3 packing (MSE-only, 3-bit split).
But it's still instantiated for turbo4 which uses different block layout.
Result: turbo4 cache writes are corrupted.

### 2. HIGH: SET_ROWS drops tail blocks when nk0 not multiple of 4
Integer division n_groups = nk0 / 4 drops remainders.
For dk=192: nk0=6, only 4 blocks processed (last 2 dropped).
Only affects non-128 head dims. Qwen uses 128 so this doesn't bite us yet.

### 3. CRITICAL: TURBO_D = QK_TURBO3 = 32 breaks turbo4 C code
The C code uses TURBO_D for array sizes. Now 32 instead of 128.
Turbo4 CPU paths have out-of-bounds array access.

## Fix
- #1: Separate turbo3 and turbo4 SET_ROWS kernel instantiations
- #2: Add assertion nk0 % 4 == 0 or handle remainder
- #3: Change TURBO_D to 128 (always), independent of QK_TURBO3

Developer Debate & Comments

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Adjacent Repository Pain Points

Other highly discussed features and pain points extracted from TheTom/turboquant_plus.

Extracted Positioning
turbo3 quantization for LLM KV cache compression
Achieving 4.6x compression with quality (perplexity, KL divergence, NIAH) comparable to q8_0 (within 2% PPL) and superior to q4_0, while maintaining high inference speed.
Top Replies
TheTom • Mar 25, 2026
## CRITICAL: Perplexity test reveals quality failure | Cache | PPL | vs f16 | |-------|-----|--------| | f16 | 6.121 | baseline | | q8_0 | 6.111 | -0.16% | | q4_0 | 6.142 | +0.34% | | **turbo3** | ...
TheTom • Mar 25, 2026
## Root causes found ### 1. V cache in rotated space Python verification: dequant output has cosine=0.02 with input (garbage). After inverse rotation: cosine=0.987 (correct). V cache values MUST be...
TheTom • Mar 25, 2026
## QUALITY FIXED ✅ Perplexity with inverse rotation restored in dequant: | Cache | PPL | vs q8_0 | |-------|-----|---------| | f16 | 6.121 | — | | q8_0 | 6.111 | baseline | | q4_0 | 6.142 | +0.5% ...
Extracted Positioning
`turbo3` decode performance for LLM inference on Apple Silicon (M1, M2 Pro, M5 Max), specifically addressing the 'decode cliff' at increasing context depths.
Achieving flat, high-performance `turbo3` decode ratios (0.90x+ of `q8_0`) across all context depths on Apple Silicon, minimizing performance degradation from memory access patterns.
Top Replies
TheTom • Mar 27, 2026
## M2 Pro Results: Bit-Arithmetic Dequant **Hardware:** Apple M2 Pro, Apple8 (1008), has_tensor=false, 32GB **Model:** Qwen2.5-7B-Instruct-Q4_K_M **Build:** experiment/m1-m2-decode-comparison (auto...
TheTom • Mar 27, 2026
## M2 Pro Results Update: Batched Extract IS a Win True baseline comparison (same branch chain, same build): | Depth | q8_0 | Main (const LUT) | Batched extract | Bit-arithmetic | |-------|------|-...
TheTom • Mar 27, 2026
## BREAKTHROUGH: Profiling isolation identifies exact bottleneck Added TURBO_PROFILE_MODE (0-4) to strip away dequant layers one at a time. ### M5 Max vs M2 Pro at 8K context decode: | Mode | What ...
Extracted Positioning
TurboQuant (`-ctk turbo3 -ctv turbo3`) integration with Vulkan devices for LLM inference.
Achieving broad hardware compatibility for TurboQuant, specifically extending to Vulkan-enabled AMD GPUs.
Extracted Positioning
TurboQuant (turbo3 and turbo4) performance optimization for LLM inference, specifically on Apple M1 hardware.
Achieving superior LLM inference speed (tokens/sec) through TurboQuant optimizations on Apple Silicon (M1).
Extracted Positioning
TurboQuant's quantization strategy, specifically regarding K/V norm disparity, attention quantization methods (MSE vs. Prod), and outlier detection (dynamic vs. fixed).
Advancing TurboQuant's quantization efficacy to achieve lower perplexity (PPL) and higher compression (lower average bit rates) through refined techniques.

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