Simten, a hardware description language (HDL) in TypeScript for browser-based simulation.

I mostly wanted to prototype hardware ideas quickly, with as little as possible between writing a circuit and watching it run. There are already solid embedded HDLs in general-purpose languages i.e. Chisel (Scala), Amaranth (Python), SpinalHDL. They all also have their own simulators, but they live inside the JVM or Python toolchains. I wanted something I could open in a browser and just start building, with nothing to install. If anyone is familiar with the game Turing Complete on Steam it was a big inspiration behind this. I just hated having to wire the gates manually.Simten is a hardware description language that's plain TypeScript. A circuit is a typed value you simulate cycle by cycle, in node or the browser, with an interactive view you can drill into and toggle back and forth across cycles. There's nothing to install to see it run, and a circuit drops into a web page as a live component. It still exports Verilog for the existing primitives (very early, flat module) when you want to take a design further. Also since it is TS, you can do cool things like use existing libs from npm and integrate them into the simulation at compile time i.e. load in data, bake it into the ROM and then run it. The figlet example on the landing page hero shows this in action.There is also an MCP that allows you to build with Claude and push to the browser locally (I know most probably won't want to learn the syntax).As for what I have done with it so far:- snake/pong at the gate level (actually harder than it sounds!)- rv32i (risc-v) CPU that is able to run C/C++/Rust compiled with GCC/rustc- run the output verilog (alongside a few board-specific extras) through the OSS FPGA toolchain i.e. Verilog -> Yosys -> nextPNR -> flashed and running on my ULX3SInterested to hear what you think and if people would actually use it. I was thinking the interactive aspect of it could be useful in CS courses. So letting students see pipeline hazards happening cycle by cycle instead of a static example in a textbook.- simten.dev/circuit (the playground to write/simulate circuits)- simten.dev/cpu/rv32i (the RISC-V CPU you can step through)- github.com/simtenHQ/simten — the repo